{"id":652,"date":"2026-10-09T01:18:16","date_gmt":"2026-10-09T01:18:16","guid":{"rendered":"https:\/\/powertechguide.com\/?p=652"},"modified":"2026-10-14T00:43:18","modified_gmt":"2026-10-14T00:43:18","slug":"multicore-embedded-system-design-mpc5748g","status":"publish","type":"post","link":"https:\/\/powertechguide.com\/en\/multicore-embedded-system-design-mpc5748g\/","title":{"rendered":"Multicore Embedded System Design Using NXP MPC5748G"},"content":{"rendered":"\t\t<div data-elementor-type=\"wp-post\" data-elementor-id=\"652\" class=\"elementor elementor-652\">\n\t\t\t\t<div class=\"elementor-element elementor-element-70a28c1d e-flex e-con-boxed e-con e-parent\" data-id=\"70a28c1d\" data-element_type=\"container\" data-e-type=\"container\">\n\t\t\t\t\t<div class=\"e-con-inner\">\n\t\t\t\t<div class=\"elementor-element elementor-element-45530fe5 elementor-widget elementor-widget-text-editor\" data-id=\"45530fe5\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t\t\t\t\t\t\n<h2 class=\"wp-block-heading\">Introduction<\/h2>\n\n<p class=\"wp-block-paragraph\">Modern embedded systems often need to perform several tasks simultaneously. A controller may need to process input signals, update an LCD, communicate with a PC, and maintain reliable control timing.<\/p>\n\n<p class=\"wp-block-paragraph\">Running all these functions in a single software execution path can make firmware more difficult to organize and maintain. A multicore microcontroller provides an opportunity to separate major functions into independent software tasks while coordinating them through shared data, interrupts, and inter-core communication.<\/p>\n\n<p class=\"wp-block-paragraph\">In my embedded controller development work, I used the NXP MPC5748G multicore microcontroller to organize three major functions:<\/p>\n\n<ul class=\"wp-block-list\">\n<li>Signal processing and main processing<\/li>\n\n<li>LCD interface processing<\/li>\n\n<li>PC interface processing<\/li>\n<\/ul>\n\n<p class=\"wp-block-paragraph\">The system was designed around the MPC5748G&#8217;s heterogeneous three-core architecture, with a separate functional responsibility assigned to each processor core.<\/p>\n\n<p class=\"wp-block-paragraph\">This article explains the processor architecture, actual core allocation, software organization, inter-core communication considerations, and practical debugging techniques for multicore embedded system development.<\/p>\n\n<h2 class=\"wp-block-heading\">1. Understanding the NXP MPC5748G Architecture<\/h2>\n\n<p class=\"wp-block-paragraph\">The NXP MPC5748G is a 32-bit automotive and industrial-oriented microcontroller based on Power Architecture technology.<\/p>\n\n<p class=\"wp-block-paragraph\">Its heterogeneous multicore architecture consists of:<\/p>\n\n<ul class=\"wp-block-list\">\n<li>Two e200z4 processor cores, supporting operation up to 160 MHz each under specified conditions<\/li>\n\n<li>One e200z2 processor core, supporting operation up to 80 MHz under specified conditions<\/li>\n<\/ul>\n\n<p class=\"wp-block-paragraph\">The cores have different capabilities and are not three identical processors. This distinction matters when allocating software functions and evaluating system performance.<\/p>\n\n<p class=\"wp-block-paragraph\">The device also provides shared resources, including on-chip memory, interconnects, interrupt facilities, and peripherals. These resources allow the cores to work together, but they must be configured and managed correctly by the firmware.<\/p>\n\n<p class=\"wp-block-paragraph\">For a real-time embedded controller, the key design question is not simply how many cores are available. It is how to allocate functions so that the processing workload, communication requirements, and timing constraints can be managed reliably.<\/p>\n\n<h2 class=\"wp-block-heading\">2. Actual Multicore Architecture in My Design<\/h2>\n\n<p class=\"wp-block-paragraph\">In my MPC5748G-based controller, I assigned a specific software responsibility to each processor core.<\/p>\n\n<h3 class=\"wp-block-heading\">Actual Core Allocation<\/h3>\n\n<figure class=\"wp-block-image size-full\"><img decoding=\"async\" class=\"wp-image-653\" src=\"https:\/\/powertechguide.com\/wp-content\/uploads\/2026\/10\/image-15.png\" alt=\"\" \/><\/figure>\n\n<p class=\"wp-block-paragraph\">The purpose of this organization was to separate the main processing path from display-related operations and PC communication.<\/p>\n\n<h2 class=\"wp-block-heading\">3. Core 0 \u2014 Signal Processing and Main Processing<\/h2>\n\n<p class=\"wp-block-paragraph\"><strong>Processor:<\/strong> e200z4<\/p>\n\n<p class=\"wp-block-paragraph\">Core 0 is responsible for signal processing and the main processing functions.<\/p>\n\n<p class=\"wp-block-paragraph\">This is the primary processing area of the controller. It handles the central application logic and coordinates the functions needed for the system to operate as intended.<\/p>\n\n<p class=\"wp-block-paragraph\">Depending on the implemented firmware, main processing can include:<\/p>\n\n<ul class=\"wp-block-list\">\n<li>Processing input signals and control conditions<\/li>\n\n<li>Executing the main application logic<\/li>\n\n<li>Managing operating parameters<\/li>\n\n<li>Coordinating controller functions<\/li>\n\n<li>Preparing data or status information for other cores<\/li>\n\n<li>Handling relevant control events<\/li>\n<\/ul>\n\n<p class=\"wp-block-paragraph\">Separating the main processing function from LCD and PC-interface processing helps establish a clear software structure.<\/p>\n\n<p class=\"wp-block-paragraph\">For high-speed control applications, however, processor task allocation alone does not guarantee precise output timing. Time-critical operations may require hardware timers, dedicated peripherals, or external programmable logic such as a CPLD.<\/p>\n\n<h3 class=\"wp-block-heading\">Engineering Considerations for Core 0<\/h3>\n\n<p class=\"wp-block-paragraph\">The main processing core should be designed with attention to execution time, interrupt latency, shared-data access, and the timing requirements of the application.<\/p>\n\n<p class=\"wp-block-paragraph\">Functions that do not need to run in the main processing path should be considered for separation, provided that the additional communication and synchronization overhead does not outweigh the benefits.<\/p>\n\n<h2 class=\"wp-block-heading\">4. Core 1 \u2014 LCD Interface Processing<\/h2>\n\n<p class=\"wp-block-paragraph\"><strong>Processor:<\/strong> e200z4<\/p>\n\n<p class=\"wp-block-paragraph\">Core 1 is assigned to LCD interface processing.<\/p>\n\n<p class=\"wp-block-paragraph\">The LCD interface presents operating information and configuration parameters to the user. Depending on the display design, the information may include:<\/p>\n\n<ul class=\"wp-block-list\">\n<li>Operating mode<\/li>\n\n<li>Duty-width settings<\/li>\n\n<li>Original delay<\/li>\n\n<li>Channel 1 through Channel 4<\/li>\n\n<li>System status and configuration information<\/li>\n<\/ul>\n\n<p class=\"wp-block-paragraph\">Separating display processing from the main processing core helps organize the user interface independently of the main application logic.<\/p>\n\n<p class=\"wp-block-paragraph\">For example, the main processing function may update a set of operating parameters, while the LCD interface reads the appropriate values and refreshes the display.<\/p>\n\n<p class=\"wp-block-paragraph\">The exact method of transferring those values between cores must be defined by the firmware architecture.<\/p>\n\n<h3 class=\"wp-block-heading\">Engineering Considerations for Core 1<\/h3>\n\n<p class=\"wp-block-paragraph\">Display operations can involve repeated updates, formatting, and communication with display hardware. These activities should be organized so that they do not unintentionally block other functions or create excessive shared-resource contention.<\/p>\n\n<p class=\"wp-block-paragraph\">A useful approach is to separate the display&#8217;s refresh activities from the main control logic and define when updated values become visible to the LCD task.<\/p>\n\n<p class=\"wp-block-paragraph\">The design should also consider how to handle inconsistent data if a value changes while the display task is reading it.<\/p>\n\n<h2 class=\"wp-block-heading\">5. Core 2 \u2014 PC Interface Processing<\/h2>\n\n<p class=\"wp-block-paragraph\"><strong>Processor:<\/strong> e200z2<\/p>\n\n<p class=\"wp-block-paragraph\">Core 2 is assigned to PC interface processing.<\/p>\n\n<p class=\"wp-block-paragraph\">This core provides a dedicated software area for PC communication through the implemented serial interface.<\/p>\n\n<p class=\"wp-block-paragraph\">Depending on the communication protocol and firmware, PC-interface processing may include:<\/p>\n\n<ul class=\"wp-block-list\">\n<li>Receiving PC commands<\/li>\n\n<li>Checking command format and validity<\/li>\n\n<li>Transferring configuration parameters<\/li>\n\n<li>Reporting system status<\/li>\n\n<li>Managing communication state<\/li>\n\n<li>Handling communication errors and timeouts<\/li>\n<\/ul>\n\n<p class=\"wp-block-paragraph\">The separation of PC-interface processing from the main signal-processing function helps organize communication software independently.<\/p>\n\n<p class=\"wp-block-paragraph\">For example, a PC command may be received and checked by Core 2 before the requested parameter is passed to the main processing function through a defined inter-core data structure.<\/p>\n\n<p class=\"wp-block-paragraph\">The exact sequence depends on the implemented firmware and command protocol.<\/p>\n\n<h3 class=\"wp-block-heading\">Engineering Considerations for Core 2<\/h3>\n\n<p class=\"wp-block-paragraph\">Communication software must account for incomplete messages, invalid commands, unexpected data, and interrupted communication.<\/p>\n\n<p class=\"wp-block-paragraph\">It is also important to define which core owns each configuration value and how commands are safely transferred to the core responsible for applying them.<\/p>\n\n<p class=\"wp-block-paragraph\">This prevents multiple software components from modifying the same control data without a clear synchronization policy.<\/p>\n\n<h2 class=\"wp-block-heading\">6. Why Use Three Cores for These Functions?<\/h2>\n\n<p class=\"wp-block-paragraph\">The main benefit of this architecture is functional separation.<\/p>\n\n<p class=\"wp-block-paragraph\">The three cores are assigned distinct responsibilities:<\/p>\n\n<figure class=\"wp-block-image size-full\"><img fetchpriority=\"high\" decoding=\"async\" width=\"867\" height=\"217\" class=\"wp-image-654\" src=\"https:\/\/powertechguide.com\/wp-content\/uploads\/2026\/10\/image-16.png\" alt=\"\" srcset=\"https:\/\/powertechguide.com\/wp-content\/uploads\/2026\/10\/image-16.png 867w, https:\/\/powertechguide.com\/wp-content\/uploads\/2026\/10\/image-16-300x75.webp 300w, https:\/\/powertechguide.com\/wp-content\/uploads\/2026\/10\/image-16-767x192.webp 767w\" sizes=\"(max-width: 867px) 100vw, 867px\" \/><\/figure>\n\n<p class=\"wp-block-paragraph\">This organization offers several potential benefits.<\/p>\n\n<p class=\"wp-block-paragraph\"><strong>Clear software structure:<\/strong> Each core has a defined role, making the application easier to divide into functional modules.<\/p>\n\n<p class=\"wp-block-paragraph\"><strong>Reduced functional coupling:<\/strong> Display and communication code can be organized separately from the main processing code.<\/p>\n\n<p class=\"wp-block-paragraph\"><strong>Independent task scheduling:<\/strong> Each core can execute its own software flow, subject to the firmware, interrupt, and resource configuration.<\/p>\n\n<p class=\"wp-block-paragraph\"><strong>Easier debugging:<\/strong> Problems can be investigated by examining the relevant functional area before checking interactions between cores.<\/p>\n\n<p class=\"wp-block-paragraph\"><strong>Future maintenance:<\/strong> Changes to the LCD or PC interface may be easier to manage when the interfaces between software modules are clearly defined.<\/p>\n\n<p class=\"wp-block-paragraph\">These are architectural benefits, not automatic performance guarantees. Overall performance depends on the workload, synchronization overhead, memory access, interrupt behavior, and peripheral configuration.<\/p>\n\n<h2 class=\"wp-block-heading\">7. Inter-Core Communication and Shared Data<\/h2>\n\n<p class=\"wp-block-paragraph\">Although the three cores have different responsibilities, they still need to exchange information.<\/p>\n\n<p class=\"wp-block-paragraph\">For example:<\/p>\n\n<ul class=\"wp-block-list\">\n<li>Core 0 may provide updated operating parameters to Core 1 for display.<\/li>\n\n<li>Core 2 may receive a PC command and pass validated information to Core 0.<\/li>\n\n<li>Core 0 may provide status information for Core 2 to report to the PC.<\/li>\n\n<li>Multiple cores may need access to shared configuration or diagnostic data.<\/li>\n<\/ul>\n\n<p class=\"wp-block-paragraph\">A clear communication mechanism is therefore essential.<\/p>\n\n<p class=\"wp-block-paragraph\">Depending on the implementation, inter-core communication may use shared memory, hardware-supported signaling, interrupts, or synchronization mechanisms.<\/p>\n\n<h3 class=\"wp-block-heading\">Recommended Design Principles<\/h3>\n\n<p class=\"wp-block-paragraph\"><strong>1. Define data ownership.<\/strong><\/p>\n\n<p class=\"wp-block-paragraph\">For each shared variable or data structure, identify which core is allowed to modify it and which cores are allowed to read it.<\/p>\n\n<p class=\"wp-block-paragraph\"><strong>2. Define the update protocol.<\/strong><\/p>\n\n<p class=\"wp-block-paragraph\">Use a consistent method to indicate when data is ready, when it has been consumed, and when it may be changed again.<\/p>\n\n<p class=\"wp-block-paragraph\"><strong>3. Prevent race conditions.<\/strong><\/p>\n\n<p class=\"wp-block-paragraph\">A race condition can occur when two cores access or modify shared data in an uncontrolled sequence. Use an appropriate synchronization mechanism when simultaneous access is possible.<\/p>\n\n<p class=\"wp-block-paragraph\"><strong>4. Consider memory visibility and cache behavior.<\/strong><\/p>\n\n<p class=\"wp-block-paragraph\">Where cached memory is involved, ensure that data written by one core is visible to another core as required. Follow the device and software-platform requirements for memory attributes, cache maintenance, and memory barriers.<\/p>\n\n<p class=\"wp-block-paragraph\"><strong>5. Keep communication overhead under control.<\/strong><\/p>\n\n<p class=\"wp-block-paragraph\">Frequent synchronization can reduce the benefits of separating functions across cores. Transfer only the information required by each task and choose an appropriate update frequency.<\/p>\n\n<h2 class=\"wp-block-heading\">8. Interrupts and Synchronization<\/h2>\n\n<p class=\"wp-block-paragraph\">Interrupts can be useful for notifying a core that an event has occurred or that new data is available.<\/p>\n\n<p class=\"wp-block-paragraph\">For example, an implementation might use an interrupt-related mechanism to notify another core that a PC command has been processed or that a new display-data set is ready.<\/p>\n\n<p class=\"wp-block-paragraph\">The exact mechanism must be verified against the actual interrupt-controller configuration, firmware, and hardware design.<\/p>\n\n<p class=\"wp-block-paragraph\">When designing inter-core interrupts, consider:<\/p>\n\n<ul class=\"wp-block-list\">\n<li>Interrupt priority<\/li>\n\n<li>Interrupt latency<\/li>\n\n<li>Re-entrancy and nested interrupts<\/li>\n\n<li>Data consistency before and after notification<\/li>\n\n<li>Repeated or missed notifications<\/li>\n\n<li>Synchronization between the producer and consumer of shared data<\/li>\n<\/ul>\n\n<p class=\"wp-block-paragraph\">An interrupt should not be treated as a substitute for a complete data-sharing protocol. The receiving core must still know which data is valid and how to process it safely.<\/p>\n\n<h2 class=\"wp-block-heading\">9. Relationship Between Multicore Processing and High-Speed Control<\/h2>\n\n<p class=\"wp-block-paragraph\">Multicore processing is particularly useful when an embedded controller combines main signal processing, user-interface functions, and external communication.<\/p>\n\n<p class=\"wp-block-paragraph\">However, these software functions can have different timing requirements.<\/p>\n\n<p class=\"wp-block-paragraph\">LCD updates and PC communication are often more tolerant of some processing delay than a precisely timed output pulse. A high-speed control application may therefore need a combination of software processing and dedicated hardware timing.<\/p>\n\n<p class=\"wp-block-paragraph\">Depending on the system design, hardware timers, microcontroller peripherals, or an external CPLD can be used to generate or coordinate time-critical signals.<\/p>\n\n<p class=\"wp-block-paragraph\">For a high-speed LED strobe controller, the complete timing path may include the processor, programmable logic, line-driver circuitry, and LED switching stage.<\/p>\n\n<p class=\"wp-block-paragraph\">The final timing accuracy must be measured on the actual hardware. A multicore processor&#8217;s maximum clock frequency alone does not establish the maximum achievable output frequency, minimum pulse width, or timing jitter.<\/p>\n\n<h2 class=\"wp-block-heading\">10. Practical Debugging Strategy<\/h2>\n\n<p class=\"wp-block-paragraph\">Multicore systems can be harder to debug than single-core applications because a problem may arise from task execution, shared data, interrupts, or interactions between cores.<\/p>\n\n<p class=\"wp-block-paragraph\">A structured debugging process can make the investigation more efficient.<\/p>\n\n<h3 class=\"wp-block-heading\">Step 1: Verify Each Core Independently<\/h3>\n\n<p class=\"wp-block-paragraph\">Confirm that Core 0, Core 1, and Core 2 start correctly and execute their assigned functions.<\/p>\n\n<p class=\"wp-block-paragraph\">Check startup configuration, clock settings, memory allocation, and core initialization.<\/p>\n\n<h3 class=\"wp-block-heading\">Step 2: Verify Each Interface<\/h3>\n\n<p class=\"wp-block-paragraph\">Test the signal-processing path, LCD interface, and PC communication independently before testing their complete interactions.<\/p>\n\n<p class=\"wp-block-paragraph\">This helps identify whether a fault originates in an individual function or in communication between cores.<\/p>\n\n<h3 class=\"wp-block-heading\">Step 3: Verify Shared Data<\/h3>\n\n<p class=\"wp-block-paragraph\">Inspect how configuration and status information move between cores.<\/p>\n\n<p class=\"wp-block-paragraph\">Check data ownership, update timing, synchronization, and memory visibility.<\/p>\n\n<h3 class=\"wp-block-heading\">Step 4: Verify Interrupt Behavior<\/h3>\n\n<p class=\"wp-block-paragraph\">Confirm that the configured interrupts are triggered and serviced as expected.<\/p>\n\n<p class=\"wp-block-paragraph\">Check priorities, event sequencing, repeated notifications, and any interaction with shared data.<\/p>\n\n<h3 class=\"wp-block-heading\">Step 5: Test Under Concurrent Workload<\/h3>\n\n<p class=\"wp-block-paragraph\">Run the main processing, LCD updates, and PC communication at the same time.<\/p>\n\n<p class=\"wp-block-paragraph\">Observe whether communication activity or display processing causes unexpected delays, inconsistent data, or other functional problems.<\/p>\n\n<h3 class=\"wp-block-heading\">Step 6: Measure Time-Critical Signals<\/h3>\n\n<p class=\"wp-block-paragraph\">If the application includes high-speed outputs, use an appropriately specified oscilloscope and probing setup to measure actual signal frequency, pulse width, duty cycle, propagation delay, and timing variation.<\/p>\n\n<p class=\"wp-block-paragraph\">Record measured results rather than relying only on theoretical calculations or processor clock specifications.<\/p>\n\n<h2 class=\"wp-block-heading\">11. Lessons from Actual Embedded System Development<\/h2>\n\n<p class=\"wp-block-paragraph\">This MPC5748G design demonstrates a practical way to organize a multicore embedded application around three major functional responsibilities.<\/p>\n\n<p class=\"wp-block-paragraph\">The core allocation was:<\/p>\n\n<ul class=\"wp-block-list\">\n<li><strong>e200z4 Core 0:<\/strong> Signal processing and main processing<\/li>\n\n<li><strong>e200z4 Core 1:<\/strong> LCD interface processing<\/li>\n\n<li><strong>e200z2 Core 2:<\/strong> PC interface processing<\/li>\n<\/ul>\n\n<p class=\"wp-block-paragraph\">The central design principle was to separate the primary processing function from the display and communication functions while preserving the coordination required for the complete system to operate.<\/p>\n\n<p class=\"wp-block-paragraph\">This approach can be useful in industrial controllers, instrumentation, machine-vision equipment, and other embedded applications that combine signal processing with a user interface and external communication.<\/p>\n\n<p class=\"wp-block-paragraph\">The most important engineering lesson is that multicore design requires more than assigning a function to each core. Data ownership, synchronization, memory visibility, interrupt handling, peripheral access, and timing requirements must all be considered together.<\/p>\n\n<p class=\"wp-block-paragraph\">A well-organized multicore architecture provides a strong foundation, but the final system must still be verified under realistic operating conditions.<\/p>\n\n<h2 class=\"wp-block-heading\">Conclusion<\/h2>\n\n<p class=\"wp-block-paragraph\">The NXP MPC5748G provides a heterogeneous three-core platform that can support the separation of major embedded software functions.<\/p>\n\n<p class=\"wp-block-paragraph\">In my design, e200z4 Core 0 handled signal processing and main processing, e200z4 Core 1 handled LCD interface processing, and e200z2 Core 2 handled PC interface processing.<\/p>\n\n<p class=\"wp-block-paragraph\">This allocation separated three important responsibilities: main application processing, user-interface operation, and PC communication.<\/p>\n\n<p class=\"wp-block-paragraph\">The architecture also illustrates why inter-core communication, synchronization, memory visibility, and timing verification are essential parts of multicore firmware development.<\/p>\n\n<p class=\"wp-block-paragraph\">For engineers developing complex embedded controllers, the main takeaway is straightforward: define each core&#8217;s responsibility clearly, establish reliable data-sharing rules, and verify the complete system under concurrent operating conditions.<\/p>\n<hr class=\"wp-block-separator has-alpha-channel-opacity\" \/>\n<h2 class=\"wp-block-heading\">Technical References<\/h2>\n\n<ul class=\"wp-block-list\">\n<li>NXP MPC5748G product information: <a href=\"https:\/\/www.nxp.com\/products\/MPC574xB-C-G\">https:\/\/www.nxp.com\/products\/MPC574xB-C-G<\/a><\/li>\n\n<li>NXP MPC5748G datasheet: <a href=\"https:\/\/www.nxp.com\/docs\/en\/data-sheet\/MPC5748G.pdf\">https:\/\/www.nxp.com\/docs\/en\/data-sheet\/MPC5748G.pdf<\/a><\/li>\n<\/ul>\n\n<p class=\"wp-block-paragraph\">Use the official device documentation to verify processor specifications, memory configuration, interrupt capabilities, and peripheral details for the selected device and operating conditions.<\/p>\n\n<ul class=\"wp-block-list\">\n<li><a href=\"https:\/\/powertechguide.com\/high-speed-led-strobe-controller-version-up\/\">High-Speed LED Strobe Controller Version-Up: MPC5744P vs. MPC5748G, Lattice CPLD, SIO, and Extended Duty\/Clock Range &#8211; PowerTechGuide<\/a><\/li>\n\n<li><a href=\"https:\/\/powertechguide.com\/high-speed-led-strobe-controller\/\">High-Speed LED Strobe Controller Design: NXP MPC5744P, Lattice CPLD, and Line Driver Switching <\/a><\/li>\n<\/ul>\n\n<p class=\"wp-block-paragraph\">\u00a0<\/p>\n\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t","protected":false},"excerpt":{"rendered":"<p>Introduction Modern embedded systems often need to perform several tasks simultaneously. A controller may need to process input signals, update an LCD, communicate with a PC, and maintain reliable control timing. Running all these functions in a single software execution path can make firmware more difficult to organize and maintain. A multicore microcontroller provides an [&hellip;]<\/p>\n","protected":false},"author":4,"featured_media":655,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"om_disable_all_campaigns":false,"_monsterinsights_skip_tracking":false,"postBodyCss":"","postBodyMargin":[],"postBodyPadding":[],"postBodyBackground":{"backgroundType":"classic","gradient":""},"page_builder":"","footnotes":""},"categories":[107,112,106],"tags":[118,117,17,119,115,114,113,120,116],"class_list":["post-652","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-embedded","category-project","category-read","tag-e200z2","tag-e200z4","tag-embedded-systems","tag-firmware-design","tag-lcd-interface","tag-multicore-mcu","tag-nxp-mpc5748g","tag-pc-communication","tag-signal-processing"],"aioseo_notices":[],"aioseo_head":"\n\t\t<!-- All in One SEO 5.0.3 - aioseo.com -->\n\t<meta name=\"description\" content=\"Introduction Modern embedded systems often need to perform several tasks simultaneously. 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A controller may need to process input signals, update an LCD, communicate with a PC, and maintain reliable control timing. Running all these functions in a single software execution path can make firmware more difficult to organize and maintain. A multicore microcontroller provides an Introduction Modern embedded systems often need to perform several tasks simultaneously. A controller may need to process input signals, update an LCD, communicate with a PC, and maintain reliable control timing. Running all these functions in a single software execution path can make firmware more difficult to organize and maintain. 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